Integrated circuits find application in many of today's consumer electronics, such as cell phones, video cameras, portable music players, printers, computers, etc. Integrated circuits may include a combination of active devices, passive devices and their interconnections.
Active devices, such as a metal-oxide-semiconductor field-effect transistor (MOSFET), generally include a semiconductor substrate, having a source, a drain, and a channel located between the source and drain. A gate stack composed of a conductive material (i.e., a gate) and an oxide layer (i.e., a gate oxide) are typically located directly above the channel. During operation, an inversion layer forms a conducting bridge or “channel” between the source and drain when a voltage is applied to the gate. Both p-channel and n-channel MOSFET technologies are available and can be combined on a single substrate in one technology, called complementary-metal-oxide-semiconductor or CMOS.
Scaling of the MOSFET, whether by itself or in a CMOS configuration, has become a major challenge for the semiconductor industry. Size reduction of the integral parts of a MOSFET has lead to improvements in device operation speed and packing density, but size reduction has its limits. For example, spacing between adjacent gate structures has been rapidly shrinking with transistor scaling and conventional spacer integration schemes. Unfortunately, the physical spacing left after conventional spacer formation between current-era adjacent gate structures is so small that challenges arise for pre-metal dielectric gap-fill, strain induced layer deposition, and contact masking and etching. Solutions to the before-mentioned problems have included the use of a disposable spacer, but unfortunately removal of the disposable spacer causes damage to underlying silicon and silicide layer due to required etch processes. Consequently, new methods must be developed to maintain the expected device performance enhancement from one generation of devices to the next.
Thus, a need still remains for a reliable integrated circuit system and method of fabrication, wherein the integrated circuit system allows removal of material between adjacent gate structures without damage to underlying layers. In view of the ever-increasing commercial competitive pressures, increasing consumer expectations, and diminishing opportunities for meaningful product differentiation in the marketplace, it is increasingly critical that answers be found to these problems. Moreover, the ever-increasing need to save costs, improve efficiencies, and meet such competitive pressures adds even greater urgency to the critical necessity that answers be found to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.